Complex Systems-on-a-Chip (SOCs) contain a variety of different functional modules on a single die of silicon, comprising billions of transistors. These SOCs usually contain one or more embedded processors, on-chip memories, hardware accelerators for e.g. cryptography and peripheral controllers for human interfacing like keyboard, screen, etc. All these units are interconnected via a hierarchy of buses, using different frequencies and potentially even different protocols, with dedicated bus bridges connecting these bus segments.
Overarching is a system management controller, usually connected to the main application processor that is responsible for proper power and clock supply for the SOCs, interacting with potentially off-chip voltage regulators, PLLs and clock dividers and clock gates.
FIG. 1 shows an embodiment of a state of the art SOC 11 with system management 12 connected to peripheral bus 15, clock supply 13 and voltage supply 14 connected to a plurality of modules; keyboard 114, touchpad 115, audio 116, LCD 117 and camera 118 connected to peripheral bus 15; peripheral bus 15 connected to processor bus 16 via bus bridge 119; application processor 18, RAM 19, crypto 110 and Ethernet 111 connected to processor bus 16; processor bus 16 connected to memory bus 17 via bus bridge 120; and ROM 112 and Flash 113 connected to memory bus 17.
System management for these chips also became increasingly complex, and the times of a simple On/Off/Standby are long gone. Especially for mobile devices aggressive power management is employed to extend battery life, but also systems with wall-plugged supply try to control power consumption to minimize thermal design power, thus allowing for slower fan speeds and/or more compact cases for a better user experience. Further, modern SOCs need several different clocks and voltages, which usually also require a certain sequencing. So, modern system management has a variety of tasks to handle:
control system ramp-up, i.e. switch on voltages and clocks in a specific sequence
bring system into and out of stand-by, i.e. switch off most parts of the system
again, ensure proper sequencing
parts of the system might stay in retention, i.e. prevent data loss in sleep state
stand-by also implies that the system management stays powered when the rest of the SOC is switched off (always-on domain)
react on wake-up events
fine-tune power consumption during normal operation, this comprises:
slow down or switch off clocks for system parts not currently needed
increase clock speed temporarily when processing power is needed
dynamically increase/decrease voltage in accordance with clock speed
On an abstract level, system management is a finite state machine (FSM) that stores a state vector, which may contain the system state, e.g. sleep, slow processing, high-speed processing, etc.; and reacts on inputs such as power and clock requests, wake-up events, etc.; and generates outputs such as voltage controls, clock enables, etc.
On a physical level, there are essentially two approaches to implement this FSM:
a) hard-wired as shown in FIG. 2. The state vector 25 is an array of flip-flops and combinational logic 22 processes the inputs 21 to calculate the next state 24 and generate the outputs 27 by means of output logic 26, based on current state 23.
b) as a program in an embedded processor as shown in FIG. 3: the state vector 35 is simply a place in the processor's memory 36 and software code 32 processes the input conditions to calculate next state and output vector. The processor 31 may be a dedicated small embedded processor in the system management unit or the task is handled by the main application processor along with its other tasks.Both these approaches have their advantages and drawbacks:The hard-wired FSM is small and easy to contain an always-on power domain. However, it is also fixed in functionality, in meaning of its states and their transitions. This can become problematic when adjustments become necessary, as this then requires silicon spins.The software on an embedded processor is relatively easy to adjust, adding or deleting states or transitions only requires a new program. However, an embedded processor requires a relatively large silicon area, more power and also usually a higher clock during stand-by than the hard-wired FSM would need.